This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-138485, filed May 14, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a memory system such as a DRAM which amplifies a low-level signal stored in a memory cell to read information, particularly to a data write circuit in the memory system, and a data write method.
2. Description of the Related Art
In a memory system such as DRAM, a low-level signal stored in a memory cell is amplified and information (data) is read. With an increase of the number of memory cells by a large capacity of a memory, a bit line capacitance as a node in which a sense amplifier senses data increases, and a capacitive coupling between bit lines increases. The increase of the bit line capacitance or capacitive coupling adversely affects a sense operation essential for high speed of a random cycle, and a peripheral operation. Examples of this adverse influence include a drop of sense speed or restore speed of the DRAM, and an increase of disturbance at a write time. The drop of speed and the increase of disturbance become obstacles in construction a high-speed cycle memory system. Especially in recent years, the high-speed cycle memory system has increasingly played an important role for a relay system of data transfer in a network.
Next, the bit line capacitance, and the influence of the capacitance between the bit lines with respect to the sense operation will be described.
As shown in FIG. 1, a bit line pair BL2, /BL2 to be noticed, and bit line pairs BL1, /BL1 and BL3, /BL3 disposed on opposite sides of the pair will be considered. A bit-line capacitance Cb of the bit line pair BL2, /BL2 is represented by: Cb=C+Cbb, wherein Cbb denotes a coupling capacitance of the bit line pair BL2, /BL2 with the bit lines /BL1, BL3 (adjacent bit lines) disposed on the opposite sides of the pair, and C denotes another capacitance.
Here, data exists so that, for example, xe2x80x9c0xe2x80x9d is sensed in the noticed bit line pair BL2, /BL2. In this case, the bit line BL2 changes to a low potential level, and the bit line /BL2 changes to a high potential level. In the bit line pairs BL1, /BL1 and BL3, /BL3 disposed on the opposite sides of the noticed bit line pair BL2, /BL2, xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is sensed/amplified.
At this time, FIG. 2A shows a state of an ideal potential change of the bit line pair BL2, /BL2 in a case in which the coupling is assumed not to exist. When a word line WL rises to a high potential level, data xe2x80x9c0xe2x80x9d of the memory cell is outputted onto the bit line BL2, and a sense operation is performed by a sense amplifier, the potential of the bit line BL2 largely changes to a power supply potential VSS from an intermediate potential, and the potential of the bit line /BL2 largely changes toward a power supply potential VDD.
Moreover, the potential changes of the bit line pairs BL1, /BL1 and BL3, /BL3 disposed adjacent to the noticed bit line pair BL2, /BL2 are assumed as follows. The bit line BL1 changes to a low level, and the bit line /BL1 changes to a high level. The bit line BL3 changes to the low level, and the bit line /BL3 changes to the high level. Then, by a coupling capacitance Cbb, as shown in FIG. 2B, from the ideal state shown by a broken line, the potential changes of the bit line pair BL2, /BL2 are suppressed as shown by a solid line. Therefore, time is unnecessarily required until the bit line pair BL2, /BL2 reaches a sufficient restore level.
In this situation, when the capacitance can be replaced with an effective bit line capacitance Cbeff, and the adjacent bit lines /BL1, BL3 change in a direction reverse to the potential changes of the noticed bit line pair BL2, /BL2, an excess charge is further required by the coupling. As a result, the effective bit line capacitance Cbeff is represented by:
Cbeff=C+2Cbb=Cb+Cbb
That is, it follows that the bit line capacitance further increases by xe2x80x9cCbbxe2x80x9d.
When the data is read or restored from the memory cell, the bit line capacitance increases and an excess time is only required. However, when the data is written, there is possibility that an erroneous operation is caused.
FIG. 3 is a schematic explanatory view showing that xe2x80x9c0xe2x80x9d is written in the noticed bit line pair BL2, /BL2. In the adjacent bit line pairs BL1, /BL1 and BL3, /BL3, xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is read, sensed, and refreshed. It is assumed that the bit line BL1 or BL3 changes to the low level, and the bit line /BL1 or /BL3 changes to the high level. At this time, assuming an ideal case in which there is not any coupling between the bit line pairs, the potentials of the adjacent bit line pairs BL1, /BL1 and BL3, /BL3 change as shown in FIG. 4A. That is, a low-level signal (potential) read from the memory cell is rapidly amplified at a timing tS in response to the operation of the sense amplifier, and stored information of the memory cell is refreshed.
On the other hand, when the capacitance between the bit lines is large, and there is the coupling of the potential change, the potential changes as shown in FIG. 4B. It is assumed that xe2x80x9c0xe2x80x9d is forcedly written in the noticed bit line pair BL2, /BL2 from the outside. At this time, the bit line /BL2 changes to the high level, and the bit line BL2 changes to the low level. In this case, when the data is transferred from the outside in a stage as early as possible, the write can be performed at a high speed.
However, when the data is transferred from the outside in this early stage, the micro read potentials from the memory cells in the adjacent bit line pairs BL1, /BL1 and BL3, /BL3 are reversed by the coupling. At a sense start time, the sense operation is performed at the potential generated by the coupling, not the read potential from the memory cell. As a result, an erroneous sense is caused with respect to the adjacent bit line pairs BL1, /BL1 and BL3, /BL3.
To solve the problem, when the sense operation of the adjacent bit line pairs BL1, /BL1 and BL3, /BL3 sufficiently proceeds, and the sense operation is not reversed any more by the coupling, the forced write needs to be performed with respect to the noticed bit line pair BL2, /BL2. However, in this case, the excess time is required for the write, and the data cannot be written, immediately after a word line WL is raised to the high level and the memory cell is selected.
Additionally, for data transfer via a high-speed network, it has increasingly become important to perform a random cycle at a high speed, and a system referred to as late write has been employed.
FIG. 5 is a schematic diagram showing an outline of specifications of the late write system. The DRAM includes cycles of write and read, and the order in which these cycles are generated is totally random. FIG. 5 shows these cycles along a time axis time, and address and data accessed at this time in each cycle are combined/shown. It is imaged that the data is taken into the memory by an arrow directed into a block at a write time, and it is imaged that the data is outputted from the memory by an arrow directed to the outside from the block at a read time.
In the late write operation, the taken data to be written is not transferred to the memory cell in the cycle, and the address and data are temporarily stored in a portion (register) other than the memory cell. In FIG. 5, an address Add1 and data Data1 are held in the register. The held address Add1 and data Data1 are transferred to the memory cell in a write cycle which soon comes next. In this manner, the address and data in the previous write cycle are transferred to the memory cell in the cycle at the present time. Since the address of a transfer destination is already known, the transfer operation can be started without waiting until the address inputted in this cycle is decided. Therefore, in principle, a write operation can be performed at the same cycle time as the read cycle time.
However, when the coupling between the bit line pairs is strong as described above, the erroneous operation of the adjacent bit line pair is caused. Therefore, the data transfer into the memory cell has to be retarded. Therefore, valuable advantages of the late write operation cannot effectively be used.
As one method of solving the problem, a method of only momentarily disconnecting the sense amplifier from the bit line at the sense operation time has been proposed. This method will be described with reference to FIGS. 6, 7A, and 7B.
As shown in FIG. 6, sense nodes S1, /S1, S2, /S2, S3, /S3 are constituted to be disconnected from bit line pairs BL1, /BL1, BL2, /BL2, BL3, /BL3 by switches SW1, /SW1, SW2, /SW2, SW3, /SW3, respectively. These switches SW1, /SW1, SW2, /SW2, SW3, /SW3 are opened (off state), when a control signal ISO has the low level. The sense nodes S1, /S1, S2, /S2, S3, /S3 are disconnected from the bit line pairs BL1, /BL1, BL2, /BL2, BL3, /BL3, respectively.
Here, xe2x80x9c0xe2x80x9d is forcedly written in the noticed bit line pair BL2, /BL2. The sense node S2 largely changes to the low level, and the sense node /S2 largely changes to the high level. Additionally, in the adjacent bit line pairs BL1, /BL1 and BL3, /BL3, the sense nodes /S1, /S3 change to the high level, and the sense nodes S1, S3 change to the low level. Such sensed and amplified situation is considered.
A sense situation of the adjacent bit line pairs BL1, /BL1 and BL3, /BL3 in a case in which there is no write is as shown in FIG. 7A. When the word line WL is raised at the high level, and the data of the memory cell is transmitted and set to the sense nodes S2, /S2 from the bit line pair BL2, /BL2, the control signal ISO is lowered at the low level, and the bit line pairs are disconnected from the sense amplifiers respectively. The sense amplifier is driven in this state, and the data is sensed and amplified. Moreover, when the data is amplified at a certain degree, the control signal ISO is raised at the high level, and the sense data is written back into the bit line pair. At this time, in the sense node /S1 or /S3, S1 or S3, the amplified level somewhat decreases. In the bit line pair BL1 or /BL3, BL1 or BL3, the level of the data of the memory cell is enlarged to the amplified level. Finally, both levels agree with each other and the data of the memory cell is restored.
The write into the noticed bit line pair BL2, /BL2 is further assumed in this operation as shown in FIG. 7B. While the control signal ISO is in the low level, that is, while the switch of the sense amplifier and bit line pair is off, the forced write is performed in the sense nodes S2, /S2 of the noticed bit line pair BL2, /BL2. Since a small coupling capacitance can be set between the amplified sense nodes of the sense amplifier, this forced write does not cause the sense erroneous operation of the amplified sense amplifier.
Therefore, the sense operation related with the adjacent bit line pairs proceeds in the same manner as in FIG. 7A. When the control signal ISO is raised at the high level, and the sense nodes S2, /S2 are connected to the bit line pairs BL2, /BL2, the noticed bit line pair changes to a forced write level, the adjacent bit line pairs change to a sense amplification level, and the write and refresh operation of the data are completed.
When the switch is disposed between the bit line pair and sense amplifier as described above, and even when the coupling between the bit line pairs is large, the data can forcedly be written at an earlier time, and features of specifications of the late write can be achieved.
However, even with this control, when the data is accessed at a high-speed cycle, it is difficult to take the timing of the control signal ISO. Also for the timing of the forced write, the data cannot be written until the data of the memory cell is sufficiently transferred to the sense node and set. A loss of timing is generated as shown by a waste time (WT) in FIG. 7B.
As described above, in the related-art memory system and data write method, with the increase of the number of memory cells by the large capacity of the memory, the bit line cycle and capacitive coupling increase, and the sense operation and peripheral operations essential for accelerating the random cycle are adversely affected.
Moreover, to transfer the data via the high-speed network, the system referred to as the late write is employed. However, when the coupling between the bit lines is strong, the erroneous operation of the adjacent bit line is caused. Therefore, the data transfer to the memory cell has to be delayed, and the valuable advantage of the late write cannot effectively be used.
As one method of solving the problem by the late write system, the method of only momentarily disconnecting the sense amplifier from the bit line at the sense operation time has been proposed. However, it is difficult to take the timing of the control signal. For the timing of the forced write, the data cannot be written until the data of the memory cell is sufficiently transferred to the sense node and set. The loss of timing is generated.
According to one aspect of the present invention, there is provided a memory system comprising: a memory cell array; a sense amplifier circuit which senses and amplifies information stored in memory cells in the memory cell array; a write circuit which writes external input data in the memory cell; a level setting circuit which sets the external input data to substantially the same level as a read potential difference level from the memory cell; a column decoder which selects a sense amplifier in the sense amplifier circuit and which selects a column of the memory cell array; a data line to transfer the external input data whose level is set in the level setting circuit to the sense amplifier selected by the column decoder; and a sense amplifier control circuit which activates the selected sense amplifier so as to write the external input data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.
Moreover, according to another aspect of the present invention, there is provided a data write method of a memory system, comprising: selecting a sense amplifier in a sense amplifier circuit which senses and amplifies information of a memory cell; setting external input data to substantially the same level as that of a read potential difference; inputting the level-set data into the selected sense amplifier via a data line; and activating the selected sense amplifier to sense, amplify, and write the data into the memory cell with substantially the same sequence as that at a data read time from the memory cell.
Furthermore, according to another aspect of the present invention, there is provided a data write method of a memory system which comprises a plurality of memory cells and in which an operation of accepting data from the outside and a transfer operation of the data into the memory cell are temporally independent, the method comprising: allowing a data read sense/restore operation from the memory cell and a data write store operation into the memory cell to substantially simultaneously proceed with respect to the different memory cells; and setting a transfer signal amount into a sense node to be sensed in the sense operation from the memory cell immediately before sensing the data to substantially the same level as that of the transfer signal amount of write data from a data acceptance portion into the sense node immediately before sensing the data to write the data.